On-Chip Permutation Mesh Network for MPSOCs Network-on-Chip
Abstract
Conversion of 2D NoC into three dimensional 3D NoC has been proposed and the 3D Networks-on-Chip (3D NoCs) have been attracted an interest to solve on-chip communication demands for future multipurpose systems. In this paper, a brief idea of 3D NoCs optimization techniques of modeling and evaluation of alternate Noc topologies, routing algorithms and mapping techniques are presented to achieve optimized area and power.
Index Terms— Network on chip; area; power; On chip communication.
Full Text:
PDFCopyright (c) 2016 P Vinaya Sri Lakshmi
This work is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International License.
All published Articles are Open Access at https://journals.pen2print.org/index.php/ijr/
Paper submission: ijr@pen2print.org