On-Chip Permutation Mesh Network for MPSOCs Network-on-Chip

Abstract

Conversion of   2D NoC  into three dimensional 3D NoC  has been proposed and the 3D  Networks-on-Chip (3D NoCs) have been attracted an interest to solve on-chip communication demands for future multipurpose systems. In this paper, a brief idea of  3D NoCs optimization techniques of modeling and evaluation of alternate Noc topologies, routing algorithms and mapping techniques are presented to achieve optimized area and power. 

Index Terms— Network on chip; area; power; On chip communication.