A Novel Method for UVM & BIST Using Low Power Test Pattern Generator

Abstract

This project describes a design of low-power (LP) programmable generator capable of producing pseudo random test pattern generator (PRPG) with desired toggling levels, code coverage and functional coverage using Universal Verification methodology (UVM). It is comprised of a linear finite state machine (a linear feedback shift register (LFSR) or a ring generator) driving an appropriate phase shifter and it comes with a number of features allowing this device to produce binary sequences. In the Built In-Logic-Block Observation (BILBO), the require consideration of time and power is not desirable.so we are introducing a self-testing using MISR and parallel SRSG (STUMPS) architecture. Furthermore, this project proposes an LP test pattern generator comparison method that allows shaping the test power envelope in a fully predictable, accurate, and flexible fashion by adapting the STUMPS-based logic BIST infrastructure over conventional method. The proposed LPPRPG is designed using Verilog HDL and functional coverage is verified by using System Verilog and UVM.

Keywords: built-in–self-test (BIST); LP (low-power) test; pseudo random pattern generator (PRPG); STUMPS; System Verilog; Universal Verification Methodology (UVM).