Digital and parallel distributed arithmetic parallel-prefix adder residue number system for reverse converter

SK. Mujafar Ahmed, Pakalapati Mounika, Boggarapu Kantha Rao


In this brief, the design of reverse converter using parallel prefix adder based multiplier for residue number system is proposed. Nowadays the parallel prefix adders are not used even though it provides significant delay reduction and high speed operation because of higher power consumption. The novel specific hybrid parallel prefix adder components that compensate the delay and power consumption in the existing system is applied to design the reverse converter. Different parallel adder structures are analyzed among that the Brent Kung prefix network is used for the parallel prefix addition because of the minimum fanout. In the proposed system the high speed parallel prefix adder is designed for modulo (4n+1) addition for n=5 and thereby designing the multiplier by using the shifting operation in the same design.

Keywords: Digital arithmetic; parallel-prefix adder (PPX); residue number system (RNS); parallel distributed arithmetic convolution architecture; reverse converter.

Full Text:


Copyright (c) 2016 SK. Mujafar Ahmed, Pakalapati Mounika, Boggarapu Kantha Rao

Creative Commons License
This work is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International License.


All published Articles are Open Access at 

Paper submission: