Design of Adaptive Triggered Flip Flop Design based on a Signal Feed-Through Scheme

Abstract

In this paper, a new explicit pulse triggered flip-flop (P-FF) design is implemented and simulated in GENERIC-TDK 130-nm technology. This explicit pulse triggered flip flop consist of a pulse generator and a true single phase clock latch based on a signal feed through scheme. The pulse generator is built with two CMOS inverters along with transmission gate logic which reduces the complexity of the circuit. The Pulse generation logic used in the explicit mode by a single pulse generator is shared for many number of flip flop at a time result in reduction of power not only this overall transistor count and delay can also been reduced. The transistor count has been reduced from 24 transistors to 16 transistors and power dissipated is 21.2133u watts. And this flip flop can achieve better D-Q delay and by using this explicit pulse triggered flip flop a synchronous counter is constructed and power dissipated is very less i.e. 19.928 nwatts.

Keywords— flipflop; to reduce no; of transistor; delay; power