Design of Digit-Serial FIR Filters using CSD Adder Graph Multiplier

Abstract

Finite Impulse Response (FIR) filters are widely applied in multi-standard wireless communications. A novel efficient algorithms and architectures have been introduced for the design of low complexity bit-parallel multiple constant multiplications (MCM) operation which dominates the complexity of many digital signal processing systems. In digit-serial MCM design that offers low complexity MCM operations that offers a low delay. In this previous design a MCM operations performed by CSE algorithm. A new greedy CSD adder graph multiplier based algorithm based on Canonic Signed Digit (CSD) representation of coefficients multipliers for implementing low complexity higher order FIR filters.