A Survey on Modular & hybrid multiplication using carry saves adder

Abstract

Low power and High-speed computing systems have been very much demand in recent years, because of the fast growing technologies in scientific computing applications. Designing a low power and high speed multiplier will have a large impact on applications like Image Processing, Convolution, Fast Fourier Transform, and Filtering and in microprocessors. The sutra named Urdhva-Triyagbhyam (Vertically and Cross wise) from the Ancient Indian Vedic Mathematics used in multiplication process since it has a unique way of calculations. Urdhvatiryakbhyam Sutra is most efficient Sutra giving minimum delay for multiplication of all types of numbers, either small or large. By using this sutra the partial products and sums are generated in one step which reduces the design of architecture in processors. Also, building an ALU using Vedic Multiplier is less complex when compared to Montgomery modular multiplier. In Montgomery modular multiplierwhile implementing two 32 bit values will produce a partial output. In the proposed Vedic Multiplier while implementing two16 bit values will produce a complete 32 bit output. As a result of this algorithm the speed of the computation process is increased and the computing time is reduced due to decrease of path delay compared to the Montgomery modular multiplier. The multiplier that has been used in a Vedic Multiplier built using urdhvaTiryakbhyam Sutra and has been fitted into the MAC design. The design of the Vedic Multiplier is performed in Veriloglanguage and the tool used for simulation is Xilinx Spartan 3.