DESIGN AND IMPLEMENTATION OF AN MULTIPLIER USING HYBRID CARRY TECHNIQUE

Abstract

In a typical processor, Multiplication is one of the basic arithmetic operations and it requires substantially more hardware resources and processing time. In computersS-MB, a typical central processing unit devotes a considerable amount of processing time in implementing arithmetic operations, particularly multiplication operations. In this paper, multiplier is done for low power requirement and high speed with Hybrid Carry Technique to improve the speed, area parameters of multiplier.