Design a Multiplier Using D.L Technique

Abstract

This paper presents the design a dual logic level [D.L] multiplier for 32*32 bit number multiplication. Modern computer system is a dedicated and very high speed unique multiplier. Therefore, this paper presents the design a dual logic level multiplier. The proposed system generates M,N and interconnected blocks. By extending bit of the operands and generating an additional product the dual logic level multiplier is obtained. Multiplication operation is performed by the dual logic level is efficient with the less area and it reduces delay i.e., speed is increased.