Algorithm and Architecture for 16*8 parallel pipeline using cam

Abstract

We propose a low-power content-addressablememory (16*8-CAM) employing a new algorithm for associativitybetween the input tag and the corresponding address of theoutput data. The proposed architecture is based on a recentlydeveloped sparse clustered network using binary connections thaton-average eliminates most of the parallel comparisons performedduring a search. Therefore, the dynamic energy consumptionof the proposed design is significantly lower comparedwith that of a conventional low-power 16*8- CAM design. Given aninput tag, the proposed architecture computes a few possibilitiesfor the location of the matched tag and performs the comparisonson them to locate a single valid match.