Low-Power And Area-Efficient Modified Carry Select Adder With Single Rca & Bec

Abstract

The increase in the popularity of portable systems as well as the rapid growth of the power density in integrated circuits have made power dissipation one of the important design objectives. Adders are one of the most widely used components in integrated circuits(ICs), designing such efficient adders has been the goal in Very Large Scale Integrated (VLSI) design. Design of area and power efficient high speed data path logic systems are one of the most substantial areas of research in VLSI system design. In every digital adder, time required for the propagation of a carry through the adder decides the speed of the addition operation. The sum for each bit position in an adder is generated sequentially only after the previous bit position has been summed and a carry propagated into the next position. The Carry Select Adder (CSA) is used in many computational systems to alleviate the problem of carry propagation delay by independently generating multiple carries and then select a carry to generate the sum. However, the Carry Select Adder is not area efficient because it uses multiple pairs of ripple carry adders to generate partial sum and carry by considering carry input and then the final sum and carry are selected by the multiplexers. The basic idea of this paper is to use binary to excess converter instead of Ripple Carry Adder (RCA) with in the regular CSA to achieve lower area and power consumption. The main advantage of this Binary to Excess Converter (BEC) logic comes from the lesser number of logic gates than the bit full adder structure.