A Novel Discrete cosine transforms & Distributed arithmetic

Abstract

In this paper, first a comparative simulation study of PSNR is done for two quantization tables, one recommended byJPEG committee and another suitable for hardware Simplification. Simulation results indicate that quantization table suitable for hardware simplification can be used fordesigning JPEG baseline coder circuitry. Then we present asimple finite state machine (FSM) based VLSI architecture andits FPGA implementation from discrete cosine transform (DCT)to zig-zag ordering of transformed coefficients for JPEGbaseline coder. 1-D DCT implementation is done for thecompressed distributed arithmetic (DA) algorithm reported in previous literature with shifting performed by division operator. Quantizer using only shifter (no adder) and 2-D DCT a recombined in single step. Implementation is done on XC2VP30device on Xilinx Virtex-II Pro FPGA board.