Error detection and correction technique for Memory applications

Abstract

In Advanced digital communication, the testing of Memory System is more complicated. As the technology, dimensions and operating voltages of the computer electronics are reduced to satisfy the consumer’s which leads to soft errors. The detection and correction of soft errors in the memory system is more susceptible. To protect memory cells from soft errors, we need more Advanced Errors correction codes. One-step Majority of Logic Decodable codes is suitable for Memory Application to detect and correct large number of errors during communication. One type of Euclidean Geometry Low – Density Parity Check (EG-LPDC) Codes are used for Error correction, because it has fault- secure detector capability. In this paper, an Enhanced Majority Logic Decoder/Detector (MLDD) is proposed to detect silent data errors (SDE) using additional logic and in order to reduce the area of Majority gate, the Sorting Network is designed. Thus, the proposed Method reduces the decoding time, area and power consumption. Hence the proposed Method Simulation Results are Shown as Power saving & Area Utilization compared to existing Method (One-step Majority of Logic Decodable codes).