An Processors With High speed OFDM & FFT size greater than 512 points with Low power consumption standards

Abstract

This paper proposes a shared multiplier scheduling scheme (SMSS) for area-efficient expeditious Fourier transform (FFT)/ inverse FFT processors. SMSS can significantly reduce the total number of involute multipliers up to 28%. The proposed commixed-radix multipath delay commutator processors can fortify 128/256 and 256/512-point FFTs utilizing SMSS. The proposed processors have been designed and implemented with 90-nm CMOS technology, which can reduce the total hardware intricacy by 20%. The proposed processors having eight-parallel data paths can achieve a high throughput rate up to 27.5 GS/s at 430 MHz. In integration, the proposed processors can fortify any FFT size utilizing adscititious stages.Lesser delay With High speed &Low  power consumption