Design of Parallel Prefix Adders Using Reversible Logic Gates

Abstract

The focus of this paper is the actual implementation of parallel prefix adders and verifies the functionality of the adder for arithmetic and logical operations used in processors and for D.S.P applications. The parallel prefix adders we mainly have are Parallel prefix adders (PPA) have the better delay performance. This paper investigates four types of PPA’s (Kogge Stone Adder
(KSA), Spanning Tree Adder (STA), BrentKung Adder (BKA) and Sparse Kogge Stone Adder (SKA)).Of all these adders we mainly focus on hybrid parallel prefix based components block instead of full adder circuits reversible gates are used such that high power consumption problems can be reduced.