High Speed Reliable Multiplier Design with Adaptive Hold Logic

Abstract

Digital multipliers are many of the maximum critical mathematics functional units. The performance of these systems generally depends on the throughput of the multiplier. Whereas, effects in the negative bias temperature stability WDNHV SODFH  ZKLOH  D S026  WUDQVLVWRU LV  XQGHUQHDWK WHUULEOH  ELDV    9JV    í9GG   LQFUHDVLQJ  WKH HGJH   YROWDJH RI WKH S026 transistor, and decreasing multiplier speed. A comparable phenomenon, positive bias temperature instability occurs while an nMOS transistor is in positive bias. Each consequence degrades the transistor speed, and inside the long term, the device may additionally fail due to timing violations. Consequently, it is crucial to layout dependable high-performance multipliers. On this paper, we suggest an high-speed multiplier design with a AHL circuit.  Due to the variable latency multiplier has higher throughput and the AHL circuit degrade overall performance . Moreover, CBM can be used in the proposed structure.