Finite Impulse Response by Filter Reconfigurable Implementation by Field Programmable Gate Array Arithmetic

Abstract

In signal processing, a digital filter is a system that performs mathematical operations on a sampled, discrete-time signal toreduce/enhances certain aspects of that signal. A digital filter usually contains of an ADC to sample the input signal, it is continued by amicroprocessor and the peripheral components such as memory to store data and filter coefficients etc. In some of the high performanceapplications, instead of using a general purpose microprocessor, FPGA or ASIC can be used for expediting operations such as filtering.One type of digital filter is FIR filter which is stable and gives linear phase response. For an Nth order FIR filter, the generation of eachoutput sample takes N+1 MAC operations. Memory based structures are well-suited for many DSP algorithms, which includesmultiplication with a set of coefficients which remains fixed. For this purpose, Distributed Arithmetic architecture is used in FIR filter.Distributed arithmetic is one way to implement convolution without the multiplier unit, where the MAC operations can be replaced by aseries of LUT access and summations. LUT are the kind of logic that used in DRAM based FPGAs. It is mainly used in the applicationslike Software Defined Radio (SDR), Digital up/down converters, Multi-Channel filters where the coefficients are changed during therun time. Hence LUT’s are needed to be reconfigurable. This project achieves high-throughput by implementing the reconfigurable FIRfilter using modified Distributed Arithmetic (DA) based approaches. For this implementation of reconfigurable FIR filter RAM basedLUT’s are used, and the implementation of such LUT’s remains costlier. Thus a shared LUT design is proposed for reconfigurable FIRfilter. Requirement of separate registers are eliminated by sharing the registers for different bit slices. Thus the DRAM based FIR filterreduces the number of bit slices. The proposed design is implemented in Xilinx Virtex-5 FPGA device (XC5VSX95T-1FF1136).