Design of B-Encoder and Decoder Using Booth Multiplier

Abstract

This paper presents the design of an encoder using booth multiplier for high security purpose. The speed of multiplier operation is of fastidious importance within the general purpose processors. The essential multiplication principle is a twofold i.e., evaluation of the partial products and accumulation of the shifted partial products with the motivation to Booth’s algorithm. In this paper, an efficient design of modified Booth Encoder and Decoder scheme for high performance of multiplier has been proposed. The proposed Booth encoder and Decoder logic are competitive with the present schemes and shows enhancements in delay. The proposed system generates B, A and interconnected blocks by extending bit of the operands and generating an additional product for an encoder and similar inverse operation for the decoder. Multiplication operation is performed to operate b-encoder and decoder, which is efficient with the less area and it reduces delay i.e., speed is increased.