An Innovative Method of Handling Intermittent Faults in Network-on-Chip Embedded Memory

Abstract

This paper proposes an innovative method of handling intermittent faults in Network-on-Chip (NoC) embedded memory. A SOA MAT++ test algorithm has been integrated into the NoC router and on-line test has been performed with writing and reading data from FIFO(first in first out). The technique involves repeating tests periodically to prevent accumulation of faults using SOA MAT++. The performance of the NoC are studied in terms