Designing a Less Energy and Less-Size Shift Register for VLSI Circuit Using Pulsed Handles

Abstract

This process solves the timing problem between pulsed latches by using multiple non-overlap postponed pulsed clock signals rather than the traditional single pulsed clock signal. This paper proposes a minimal-power and area-efficient shift register using pulsed latches. The architecture of the shift register is very simple. An N-bit shift register consists of series connected N data switch-flops. The rate from the switch-flop is less important compared to area and power consumption because there's no circuit between switch-flicks within the shift register.  The region and power consumption are reduced by changing switch-flops with pulsed latches. The shift register uses a small amount of the pulsed clock signals by grouping the latches to many sub shifter registers and taking advantage of additional temporary storage latches. A 256-bit shift register using pulsed latches was fabricated using CMOS process with. The suggested shift register saves area and power in comparison towards the conventional shift register with switch-flops. Lately, pulsed latches have changed switch-flops in lots of programs, just because a pulsed latch is a lot smaller sized than the usual switch-flop. However the pulsed latch can't be utilized in a shift register because of the timing problem between pulsed latches.