VLSI Architecture of FM0/Manchester Encoding Technique for DSRC

Abstract

The dedicated short-range communication (DSRC) is an evolving technology to push the smart transport system into our daily life. The DSRC technique usually adopt FM0 and Manchester encodings to reach dc-balance, boosting the signal quality. Nevertheless, the coding coordination between the FM0 and Manchester codes limits the potential to design a fully used VLSI architecture for Fm0 and Manchester. In this project, the (SOLS) technique is presented to overcome this drawback. The SOLS technique improves the hardware consumption rated from 57.14% to 100% for FM0 and Manchester codes. The projected method is capable of generating Manchester and Fm0 coding for DSRC applications.