Novel NAND NR4SD Encoding of Low Power Carry Skip adder based On Pre-Encoded Multipliers

Abstract

In this paper has  discussion about the new design of pre-encoded multiplier were explored at offline the standard co efficient and storing them in system memory. The co efficient was used in non redundant radix 4 signed digit (NR4SD) form.  The proposed NR4SD encoding scheme uses one of the following sets of digit values {-2,-1,0,+1} or {-1,0,+1,+2}. In order to cover the dynamic range of the 2’s complement form, all digits of the proposed representation were encoded according to NR4SD except the most significant bit that was MB encoded.  Pre-encoding the standard coefficients are stored into  ROM in a condensed form (i.e., 2 bits per digit). Compared to the pre-encoded MB multiplier in which the encoded coefficients need 3 bits per digit, the proposed NR4SD scheme reduces the memory size. Also, compared to the MB form, which uses five digit values {-2,-1,0,+1,+2}.This encoding technique was less complex partial product implementation, less area and more power efficient design. Analysis was verifying the proposed system was efficient from the existing system.