Review in Low Power VLSI Design

S. H. Prasad, G. Rama Naidu, G. Ajay Shankar, S.B.G. Tilak Babu

Abstract


The recent trends in the developments and advancements in the area of low power VLSI Design are surveyed in this paper. Though Low Power is a well established domain, it has undergone lot of developments from transistor sizing, process shrinkage, voltage scaling, clock gating, etc., to adiabatic logic. This paper aims to elaborate on the recent trends in the low power design.



Keywords


Multi threshold, dynamic voltage and frequency scaling, split level charge recovery logic, efficient charge recovery logic, positive feedback adiabatic logic, pre-resolve and sense adiabatic logic.

Full Text:

PDF


Bookmark and Share


Copyright (c) 2017 Edupedia Publications Pvt Ltd

Creative Commons License
This work is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International License.

 

All published Articles are Open Access at  https://journals.pen2print.org/index.php/ijr/ 


Paper submission: ijr@pen2print.org