Testing Of SRAMS Using Row and Column Address

Abstract

Memories of Flash are another type of memory of non-volatile on floating-gate transistors. The use of commodity and embedded memories of flash has rapid growth while we are entering in the system-on-chip era. Conventional tests for flash memories are usually ad hoc is the test procedure which is developed for a specific design. As there is a large number of possible failure modes for memories of flash, algorithms of long test that is automatic test equipment (ATE) which is complicated are commonly seen. Production row and column address bit cell as basis to probe for any possible weaknesses of the process or design in SRAM. There may be occurrence of sa0 and sa1 faults in any chip design, these faults are overcome by using row and column address cells we make perfect location to store the data and no cross sections of SRAMS. By extending of cell checking for memory array gives verification of memory location. The column address buffer and row address buffer are used to pick the memory location. By comparing with previous method the above two modules gives accurate selection of memory location of cell checking operation