Design of Novel Reversible Multiplier Using Ns Gate

Abstract

In digital computer system a major problem has been found that the delay and high memory usage which leads to bring some research on the methods to decrease the delay and memory usage. This is the main cause to give birth to reversible computing systems for digital computers and designs. The main aim of this reversible computing is to lower the delay and memory usage and some other advantages like security of data and prevention of errors etc... Reversible logic has so many applications low delay CMOS, nanotechnology, DNA computing and quantum computing. There are two primary design implementations in this study which are the major spotlights. The first one is reversible design gate and the second one is multiplier design using reversible gates. In this manuscript we have implemented a 16 * 16 reversible design called “NSG”. The total project is implemented in Xilinx 14.7 ISE with Spartan 3E family.