Design via DLL Multiplier Using Redundant Basis for FPGA and ASIC Implementation

Abstract

Redundant basis (RB) multipliers over Galois Field (GF (2^m)) have gained huge popularity in elliptic curve cryptography (ECC) mainly because of their negligible hardware cost for squaring and modular reduction. In this paper we discuss the growth has started the spread of architectures for implementing ECC from FPGA towards ASIC. Computing scalar multiplication and point inversion forms the core ECC architecture. ASIC based implementation of these ECC arithmetic primitives over finite fields GF (2m). we have proposed a Dual Logic Level (DLL) the arithmetic components are designed using Verilog and implemented on field programmable gate array (FPGA) and application specific integrated circuit (ASIC) realization of the proposed designs especially presented in high-throughput  up to 50% and 20% savings area-delay-power product (ADPP)  implementation over the best of the existing designs, respectively.