An Efficient VLSI Architecture of a Clock-gating Turbo Decoder

Abstract

Wireless sensor network can be considered to be energy constrained wireless scenarios, since the
sensors are operated for extended periods of time, while relying on batteries that are small,
lightweight and inexpensive. The conventional turbo decoder architecture requires high chip area and
hence high power consumption. This motivated the proposed system to design the decoder
architecture with high throughput, less decoding iteration and less memory requirement. Clock
gating is a technique that can be used to control the power dissipated by clock net. The proposed
work is implemented using clock gating technique in order to reduce the power consumption. The
previous turbo decoder architectures uses optimal-log based algorithm which has the complexity
about 75% and hence leads to time and energy consumption due to sequential operations. Where as
the proposed architecture uses the fundamental Add Compare Select (ACS) operation. Due to the
parallel processing operation of ACS blocks the proposed architecture tend to have low processing
steps, so that low transmission energy and less complexity about 71%. The proposed work
implementation has a throughput of 1.03 Mb/s, memory requirement of 128 Kbps, power
consumption of about 0.016(mV) and requires 0.010(A) of current. Comparing to the optimal-log
based algorithm in the proposed lookup table based architecture the complexity is reduced by 4%
and by implementing the clock-gating technique the power consumption is reduced by 38%.