An Efficient Architecture for 32-bit Multiply-Accumulate (MAC) Unit Using Redundant Binary Multiplier

Abstract

The multiplication and accumulation are the vital operations involved in almost all the Digital Signal Processing applications. Consequently, there is a demand for high speed processors having dedicated hardware to enhance the speed with which these multiplications and accumulations are performed. The speed of MAC depends on the speed of multiplier.Due to its high modularity and carry-free addition, a redundant binary (RB) representation can be used when designing high performance multipliers. In this paper, a new RB modified partial product generator (RBMPPG) is proposed; it removes the extra ECW and hence, it saves one RBPP accumulation stage. Here using RB modified partial product generator multiplier is used to design MAC unit.The results reveals the implementation of proposed MAC unit is efficient in terms of area and speed. Synthesis and Simulation are performed using Xilinx ISE design suit 13.2 and Modelsim respectively.