Design of Low Delay 32-Bit Parallel Prefix Brentkung Adder

Abstract

In VLSI design the excellent performance is produced by a parallel-prefix adder. Nevertheless, the performance can takes large delay through CSLA or CSA. Then, new approachgenerates the Efficiency inBrent-kungAdder. There are two stages of operation in proposed system.They are pre-processing stage and generation stage. The propagate and generate are possessed in the pre-processing stage.Generation stage concentrates on carry generation and final result. Each bit having addition operation in ripple carry adder.Then each bit can wait for the preceding bit addition operation. But the each bit does not wait for preceding bit addition operationin efficient Brent – Kung adder and modification is done at gate level to improve the speed.