Design of Hybrid LUT/MUX Based Configurable Logic Architectures for FPGAs

Abstract

New types of logic block architectures for FPGAs are designed and evaluated using Verilog to Routing (VTR) tool. Two types of architectures namely Nonfracturable and fracturable are designed. A new logic element (MUX4) is used along with conventional LUT in the proposed logic block architectures. Fracturable logic elements have achieved improved logic density. MUX4 logic element along with LUT has reduced the area consumption as compared to conventional logic block architectures. The architectures are evaluated by implementing benchmark circuits on to them by VTR tool. A new CAD flow has been generated to map the circuits on to the proposed logic structures. The usage of 50% depopulated interconnect structure inside the logic cluster has provided the area savings up to 15%. The proposed non fracturable architectures have provided the area savings up to 5% and fracturable architectures have achieved 2% area savings.