Design an High speed Digital Fault Tolerant Architecture

Abstract

In the era of deep sub-micron technology, probability of chip failure has been increased with increase in chip density. A system must be fault tolerant to decrease the failure rate and increase the reliability of it. Multiple faults can affect a system simultaneously and there is a trade-off between area overhead and number of faults tolerated. This paper presents high speed fault tolerant architecture design for digital applications. The fault containment and parallel processing capabilities of computers network are being exploited to provide a high performance, high availability network capable of tolerating a broad scope of hardware, software, and operating system faults.