Design Of Encoder And Decoder Using Hybrid Lut/Multiplexer

Abstract

In this paper, a novel architecture of encoder and decoder using high security technique for the VLSI implementation for encoder and decoder using Hybrid MUX/LUT. The pre-defined keys are required for each input for both encryption and decryption that are generated in real-time by the key-scheduler module by expanding the initial secret key and thus used for reducing the amount of storage for buffering. S-boxes are used for the implementation of the S.R, M.C and inverses S.R & M.C shared between encryption and decryption. The round keys needed for each round of the implementation are generated in real-time. The forward and reverse key scheduling is implemented on the same device, thus allowing efficient area minimization. Rather than using logical gates we are using hybrid LUT or MUX for speed of operation. The pipelining is used after each standard round makes fast of operation to enhance the throughput and shift row mix column technique gives high security.