Memory-Reduced and Area Efficient Turbo Decoding Architecture

Abstract

A new compression technique known as Next Iteration Initialization (NII) metrics is proposed for modifying the storage demands of turbo decoders. The proposed method stores only the range of state metrics with two indexes of the maximum and minimum values, whereas the previous compression methods have to store all of the state metrics for initializing the following iteration. A hardware-friendly recovery strategy is proposed which can be implemented by simple multiplexing networks. Compared to the previous work, as a result, the proposed compression method reduces the required storage bits while providing the acceptable error-correcting performance in practice. The proposed architecture of this paper can analyze the logic size and area by using Xilinx 14.3.