VLSI Design of a New High Throughput Finite Field Redundant Multiplier

Abstract

Redundant basis (RB) multipliers over Galois Field (GF (2^m)) have gained huge popularity in Elliptic Curve Cryptography (ECC) mainly because of their negligible hardware cost for squaring and modular reduction. Elliptic Curve Cryptography (ECC) is an approach to public key cryptography based on the algebraic structure of elliptic curves over finite fields. In this paper, we have proposed a novel recursive decomposition algorithm for RB multiplication to obtain high throughput digit serial implementation. Through efficient projection of Signal Flow Graph (SFG) of the proposed algorithm, a highly regular Processor Space Flow Graph (PSFG) is derived. In this project we are deriving three novel multipliers which not only involve significantly less time complexity than the existing ones but also require less area and less power consumption compared with the others. Both theoretical analysis and synthesis results confirm the efficiency of proposed multipliers over the existing ones. The synthesis results for Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) realization of the proposed designs and competing existing designs are compared. The extension for the project is Dadda multiplier. The Dadda multiplier is a hardware multiplier design similar to the Wallace multiplier, but it is slightly faster (for all operand sizes) and requires fewer gates (for all but the smallest operand sizes). Simulation and synthesis results are obtained by using Xilinx ISE 13.2, which when compared with proposed and extension results in the reduction of area, increasing the speed.