Low Latency Mixed Decimation Mdf Architecture for Fft Design

Abstract

The main objective of this project is to design a mixed-decimation multipath delay feedback (M2 DF) approach for the radix-2^k fast Fourier transform. The appearance of radix- was a milestone in the design of pipelined FFT hardware architectures. Later, radix-2^k was extended to radix-2^k. However, radix-2^k was only proposed for single-path delay feedback (SDF) architectures, but not for feed forward ones, also called multi-path delay commutator (MDC). This paper presents the radix-2^k feed forward (MDC) FFT architectures.

 In feed forward architectures radix- can be used for any number of parallel samples which is a power of two. Furthermore, both decimation in frequency (DIF) and decimation in time (DIT) decompositions can be used. In addition to this, the designs can achieve very high throughputs, which make them suitable for the most demanding applications. Indeed, the proposed radix-2^k feed forward architectures require fewer hardware resources than parallel feedback ones, also called multi-path delay feedback (MDF), when several samples in parallel must be processed.

 As a result, the proposed radix-2^k feed forward architectures not only offer an attractive solution for current applications, but also open up a new research line on feed forward structures. Vedic sutra is used as an enhancement for this project. Recursively is a main challenging factor in all arithmetic operations.  Multiplier doesn’t follow that rule until Vedic sutras comes in to picture. Urdhva Tiryakbhyam in Vedic is a main multiplication algorithm for latency reduction