Browse Title Index


 
Issue Title
 
Vol 2, No 11 (2015): VOL-2_ISSUE-11_November_2015 Low Complexity Decoding Algorithms and Architectures for Non Binary LDPC Codes Abstract   PDF
M. Sravan Kumar, A. Satheesh
 
Vol 4, No 10 (2017): Vol-04_Issue-10_September_2017 Low Complexity Linear Precoder Design For Mimo-Ofdm System Abstract   PDF
D. Swathi, K Amit Bindaj, J. Narendra Babu
 
Vol 2, No 12 (2015): VOL-2_ISSUE-12_December_2015 Low Complexity Slm Based Paper Reduction for Multiuser Stbc Mc-Cdma System Abstract   PDF
Seepana Sirisha, Tejaswi Madugula
 
Vol 3, No 17 (2016): Vol-3_Issue-17_November_2016 Low Cost And High Performance Of Vlsi Architecture For Reconfigurable Montgomery Modular Multiplication Abstract   PDF
Mandalaneni Jaya, Shaik Masthan Sharif
 
Vol 5, No 20 (2018): Vol-5-Issue-20-September-2018 Low Cost Home Automation Using Offline Speech Recognition Abstract   PDF
Poorna. R, Janani. A, Priyadarshini . K
 
Vol 2, No 5 (2015): VOL-2_ISSUE-05_May_2015 Low cost Low power Solar Based Multilevel Water Pumping for Irrigation Abstract   PDF
Ravi kumar R, Ashiwini T P
 
Vol 4, No 17 (2017): Vol-04-Issue-17-December-2017 Low Cost Object Sorting Robotic Arm Using Raspberry Pi Abstract   PDF
B.Santhosh Kumar, K.Sathish Babu
 
Vol 1, No 10 (2014): Vol-1_Issue-10_November_2014 Low Energy Bluetooth Abstract   PDF
Deepti Gill, Neeti Panchal, ms Leena
 
Vol 4, No 17 (2017): Vol-04-Issue-17-December-2017 Low Frequency Modular Multilevel Converter Topology for Improved Dynamic Performance of Variable-Speed AC Drives Abstract   PDF
G. S. R. Ajay Krishna, D. Krishna
 
Vol 5, No 4 (2018): Vol-05-Issue-04-February-2018 Low hardware Accumulator Based 3-Weight Pattern Generation for Boundary Scan Abstract   PDF
Sandeep Kumar Vasa
 
Vol 5, No 4 (2018): Vol-05-Issue-04-February-2018 Low hardware Accumulator Based 3-Weight Pattern Generation for Boundary Scan Abstract   PDF
Manthri Lavanya, K. Saifuddin
 
Vol 3, No 17 (2016): Vol-3_Issue-17_November_2016 Low Latency Low Complexity Compare and Decode Architecture for LTE Turbo Codes Abstract   PDF
Aaquib Javed, Vijay L. Agrawal
 
Vol 4, No 14 (2017): Vol-04-Issue-14-November-2017 Low Latency Mixed Decimation Mdf Architecture for Fft Design Abstract   PDF
M. HARIKA, C. ASHOK KUMAR
 
Vol 5, No 01 (2018): Vol-05-Issue-01-January-2018 Low power 16 bit ALU design using Full adder and Multiplexer Abstract   PDF
Kalla Priyanka, A. Prasad, P.Prasanna Murali Krishna
 
Vol 5, No 12 (2018): Vol-05-Issue-12-April-2018 Low power and high speed optimized 4-bit array multiplier using GDI technique Abstract   PDF
S.Velugonda Reddy, A. Prasad, K.Ranjith kumar
 
Vol 4, No 14 (2017): Vol-04-Issue-14-November-2017 Low Power Array Multiplier Using Modified Full Adder Abstract   PDF
K. Swapna, K. Vijay Kumar
 
Vol 5, No 01 (2018): Vol-05-Issue-01-January-2018 Low Power Array Multiplier Using Modified Full Adder Abstract   PDF
T.Tirupathi Rao, Mary Vijitha
 
Vol 5, No 01 (2018): Vol-05-Issue-01-January-2018 Low Power Array Multiplier Using Modified Full Adder Abstract   PDF
T.Tirupathi Rao, Mary Vijitha
 
Vol 5, No 16 (2018): Vol-05-Issue-16-June-2018 Low Power Array Multiplier Using Modified Full Adder Abstract   PDF
B. Subhakara Rao, Gentela Madhavi
 
Vol 3, No 11 (2016): Vol-3_Issue-11_July_2016 Low Power Asynchronous Domino Logic Pipeline Design Strategy Abstract   PDF
P. SRAVANTHI, P. MURALIKRISHNA
 
Vol 5, No 7 (2018): Vol-05-Issue-07-March-2018 Low Power BIST based Multiplier Design and Simulation using FPGA Abstract   PDF
MR. D. SRIDHAR, G. Kalyani, B. Veerane, Ch.L. Pavan Kumar Gupta, E. Phani Pavan Prakash, CH. Akhil Babu
 
Vol 4, No 14 (2017): Vol-04-Issue-14-November-2017 Low Power Design of Double Ended Bit-lines with Read Decoupled 8T Static RAM Cell Abstract   PDF
Devupalli Sunil Kumar, Bandi Sarada, Manas Ranjan Biswal
 
Vol 5, No 12 (2018): Vol-05-Issue-12-April-2018 Low Power Energy Conversion With Two Phase Permanent Magnet Machine And Rectifier With Reduced Number Of Controlled Switches Abstract   PDF
KANNAN. N
 
Vol 3, No 14 (2016): Vol-3_Issue-14_October_2016 Low Power Montgomery Modular Multiplication Using Carry Save Adder Abstract   PDF
M.Y. Krishna Pal, K. Suresh
 
Vol 7, No 6 (2020): Vol-7-Issue-6-June-2020 Low Power Parallel VLSI Architecture for Mbist Abstract   PDF
G SAI RAM RAJU, Mrs. K VANI
 
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