Browse Title Index


 
Issue Title
 
Vol 4, No 17 (2017): Vol-04-Issue-17-December-2017 Design of Improved Proxy Regenerating Code Based Cloud Storage System Abstract   PDF
Kandati Sindhuja, Dvss Subramanyam, Suresh Akella
 
Vol 4, No 10 (2017): Vol-04_Issue-10_September_2017 Design of Improved Reversible Data Hiding In Encrypted Images Abstract   PDF
M. RamaRao, P. Kumaraswamy
 
Vol 3, No 14 (2016): Vol-3_Issue-14_October_2016 Design of Integrated System For Bidirectional Power Flow Between the Electric Vehicle And DC or AC Grid Abstract   PDF
M. M. Irfan, Kodepaka Jerusha
 
Vol 2, No 10 (2015): VOL-2_ISSUE-10_October_2015 Design of Intelligent Embedded System for Automotive Crash Prediction Abstract   PDF
Y. Vijayalaxmi, S. Ravi
 
Vol 4, No 14 (2017): Vol-04-Issue-14-November-2017 Design Of Islanding Detection Using Phase-Locked Loops In Three-Phasegrid-Interface Power Abstract   PDF
K Gopi
 
Vol 5, No 20 (2018): Vol-5-Issue-20-September-2018 Design of Level Shifter with Wide Input Voltage Range Abstract   PDF
P Pydi Reddy, M Ashok Kumar
 
Vol 7, No 5 (2020): Vol-7-Issue-5-May-2020 Design of Light Weight Encryption Algorithm for Data Privacy in Light Weight Devices Using 128 Bit Key Abstract   PDF
Korada Yougeswari Devi, Dr. V.V.S.S.S. Chakravarthy
 
Vol 4, No 9 (2017): Vol-4_Issue-09_August_2017 Design of Low Delay 32-Bit Parallel Prefix Brentkung Adder Abstract   PDF
T. Pragna, mr. K. Ravi
 
Vol 5, No 4 (2018): Vol-05-Issue-04-February-2018 Design of Low Power & High Speed Parallel Prefix Comparator Abstract   PDF
V.Venkata Arjun, Lakshmi Prasad.Ch
 
Vol 5, No 23 (2018): Vol-5-Issue-23-December-2018 Design of Low Power 9t Sram Using Single Bit Line Abstract   PDF
ATCHA LALITHA, T.VAISHNAVI CHANDRA, D.NAGA RAVI KIRAN
 
Vol 4, No 14 (2017): Vol-04-Issue-14-November-2017 Design of Low Power Adder in ALU Using Flexible Charge Recycling Dynamic Circuit Abstract   PDF
Pallavi Mamidala, K. Anil kumar
 
Vol 3, No 17 (2016): Vol-3_Issue-17_November_2016 Design of Low Power and High Speed Digital Filter in 45nm with for Digital Signal Processing Applications Abstract
K. Rajendra Prasad, Yashpal Singh
 
Vol 3, No 17 (2016): Vol-3_Issue-17_November_2016 Design of low Power and low latency hybrid scheme for network on chip Design Abstract   PDF
B. Gowripriya, Y.L. Ajaykumar
 
Vol 4, No 7 (2017): Vol-04_Issue-07_June_2017 Design of Low Power and Low Latency Novel Scheme for Network on Chip Abstract   PDF
Y. L. Ajay Kumar, Dr. D. Satyanarayana, Dr. D. Vishnu Vardhan
 
Vol 5, No 22 (2018): Vol-5-Issue-22-November-2018 Design of low power high -performance of 2-4 and 4-16 mixed logic line decoders Abstract   PDF
G Jhansi Rani, M Mahaboob Basha
 
Vol 4, No 9 (2017): Vol-4_Issue-09_August_2017 Design of Low Speed High Power Digital Filter in Communication Systems Abstract
K. Rajendra Prasad, Yashpal Singh
 
Vol 2, No 1 (2015): Vol-2_Issue-1_January_2015 Design of Low-Power Full Adder Using GDI Structure and Hybrid CMOS Logic Style Abstract   PDF
Banda Srikanth
 
Vol 5, No 19 (2018): Vol-5-Issue-19-August-2018 Design of Maximum Power Extraction Algorithm for Sepic Converter Based Variable Speed Wind Energy Conversion Systems Abstract   PDF
J. Kishore, P. Manikanta.
 
Vol 4, No 2 (2017): Vol-04_Issue-02_February_2017 Design of Medical Data Monitoring by Using Raspberry Pi Abstract   PDF
Konala Reshma, K. Rajasekhar
 
Vol 3, No 17 (2016): Vol-3_Issue-17_November_2016 Design of Microarray Image Analysis Techniques: An Image Processing Segmentation Approach Abstract
T. Srinivas Reddy, Yashpal Singh
 
Vol 2, No 2 (2015): Vol-2_Issue-02_February_2015 Design Of Microstrip Line-Fed Compact Low Profile Rectangular Dielectric Resonator Antenna For Wireless Applications Abstract   PDF
Ratan Pal Singh, Saptadweepa Saha, Shayan Saha, Rumela Gupta, Sudipto Das Burman
 
Vol 1, No 9 (2014): Vol-1_Issue-9_October_2014 Design of Microstrip Rectangular Patch Antenna for Wireless Application Abstract   PDF
Ratan Pal Singh
 
Vol 3, No 18 (2016): Vol-3_Issue-18_December_2016 Design of Modified 64-Bit Parallel Prefix Technique B-K Adder Abstract   PDF
DONEPUDI SUMAJA REDDY, SARALA PATCHALA
 
Vol 4, No 9 (2017): Vol-4_Issue-09_August_2017 Design of Montgomery Modular Multiplication with high Performance and Reduced Area. Abstract   PDF
Boggarapu Kantha Rao, Pola Pavithra, Sk. Mujafar Ahmed
 
Vol 3, No 18 (2016): Vol-3_Issue-18_December_2016 Design of multilevel inverter topology using less number of switches Abstract   PDF
T. Naveen Kumar
 
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