Browse Title Index


 
Issue Title
 
Vol 3, No 18 (2016): Vol-3_Issue-18_December_2016 VLSI Architecture of Shared Multiplier Scheduling Scheme for Reconfigurable FFT/IFFT Processor Abstract   PDF
T. Ganesh Reddy, A. Suneel Kumar
 
Vol 7, No 6 (2020): Vol-7-Issue-6-June-2020 VLSI Architectures for 8 Bit Data Comparators for Rank Ordering Image Applications Abstract   PDF
C Satish Babu, S. Ashok Reddy, Malli karjuna
 
Vol 7, No 6 (2020): Vol-7-Issue-6-June-2020 VLSI Architectures for 8 Bit Data Comparators for Rank Ordering Image Applications Abstract   PDF
C Satish Babu, Malli karjuna
 
Vol 4, No 17 (2017): Vol-04-Issue-17-December-2017 VLSI Design and Comparison of PASTA Multiplier with Carry save Multiplier Abstract   PDF
M. Sai Lakshmi, S. Ravindra
 
Vol 4, No 9 (2017): Vol-4_Issue-09_August_2017 VLSI Design and Implementation of Arithmetic Circuit for Video Encoding Using VLSI Technology Abstract   PDF
Sk. Mujafar Ahmed, Shaik Yasmin, Boggarapu Kantha Rao
 
Vol 4, No 2 (2017): Vol-04_Issue-02_February_2017 VLSI Design and Implementation of Fast Addition Using QSD Number System Abstract   PDF
Muskaawaar Kiran, K Siva Kumara Swamy
 
Vol 3, No 14 (2016): Vol-3_Issue-14_October_2016 Vlsi Design for Carry-Protect Formatted Data Abstract   PDF
SK. MUJEEB, B. BALA KRISHNA, B. S.R. MURTHY
 
Vol 4, No 2 (2017): Vol-04_Issue-02_February_2017 VLSI Design For Carry-Protect Formatted Data Abstract   PDF
NAGULA RAVI TEJA, K.SANTHOSH KUMAR
 
Vol 4, No 11 (2017): Vol-04-Issue-11-September-2017-Special-Issue-in-UGC-Approved-Journal VLSI Design of a New High Throughput Finite Field Redundant Multiplier Abstract   PDF
A. Shravya, G. Prasad Acharya
 
Vol 4, No 17 (2017): Vol-04-Issue-17-December-2017 VLSI Design of a Novel LP-LFSR based programmable PRPG Architecture Abstract   PDF
Santhi Priya, G. Ravikishore
 
Vol 5, No 01 (2018): Vol-05-Issue-01-January-2018 VLSI Design of a Novel Pre Encoding Multiplier Using DADDA Multiplier Abstract   PDF
G.V.S.M. Kumar, E. Adinarayana, V.S.R. Kumari
 
Vol 5, No 01 (2018): Vol-05-Issue-01-January-2018 VLSI Design of a Novel Wallace Tree Multiplier for an FIR Filter Abstract   PDF
Ahtesham Ali Mir, Towfeeq Fairooz
 
Vol 5, No 01 (2018): Vol-05-Issue-01-January-2018 VLSI Design of AMBA ACE4-Lite Interconnect protocol for SOC Abstract   PDF
Chiranjeet Kumar, M. Gurunadha Babu, Suneel Laxmipuram
 
Vol 5, No 01 (2018): Vol-05-Issue-01-January-2018 VLSI Design of an Area Efficient Novel 64 Bit Reconfigurable FIR Filter Abstract
Sridevi Nerusu, R.L.R. Lokesh Babu, Dr. U. Yedukondalu
 
Vol 5, No 4 (2018): Vol-05-Issue-04-February-2018 Vlsi Design of Bit-Stream Compression Based On Run Length Encoding Abstract   PDF
N. Nandeeswari, S.Deva Karun
 
Vol 4, No 5 (2017): Vol-04_Issue-05_April_2017 VLSI design of Parallel Filters Based on Error Correction Codes for Fault Tolerance Abstract   PDF
Sudheer Chirivella, Gaddam Sekhar Reddy, Sannikanti Kishore Babu
 
Vol 6, No 12 (2019): Vol-6-Issue-12-November-2019 VLSI Design of Polynomial Weight Functions Based Cellular Network Architecture Abstract   PDF
P. S. S. T. U. Kameswari, B. Gangadhara Rao
 
Vol 5, No 12 (2018): Vol-05-Issue-12-April-2018 Vlsi Implementation Of 16 × 16-Digit Parallel Multiplier Abstract   PDF
Y. Srilakshmi, T. Lilly Prasanthi
 
Vol 5, No 01 (2018): Vol-05-Issue-01-January-2018 VLSI Implementation of AES Algorithm using Rijndael algorithm Abstract   PDF
M. Srujana, B. Parameshwari
 
Vol 4, No 2 (2017): Vol-04_Issue-02_February_2017 VLSI Implementation of Aging Aware Design for Low Power Applications Abstract   PDF
VARDHANAPU SUMA BINDU, G. AMMARAJU
 
Vol 1, No 10 (2014): Vol-1_Issue-10_November_2014 VLSI Implementation of Least Square Channel Estimation and QPSK Modulation Abstract   PDF
Ashish Bharti, Ekansh Beniwal, Himanshu Kaintura
 
Vol 2, No 11 (2015): VOL-2_ISSUE-11_November_2015 Vlsi Implementation Of N×M-Bit Rsfq Multiplier For Dsp or Multimedia Applications Abstract   PDF
Ramana Jampala, K. Swapna
 
Vol 3, No 13 (2016): Vol-3_Issue-13_September_2016 VLSI Implementation of Self Time Adder Using Recursive Approach Abstract   PDF
A. RADHIKA, M. RANJITH
 
Vol 2, No 5 (2015): VOL-2_ISSUE-05_May_2015 Vlsi Modelling of Efficient Carry Select Adder with Redundant Encoding Technique Abstract   PDF
Syed Jakeer Shareef, K. Jagadeesh Kumar, V. Thrimurthulu
 
Vol 2, No 5 (2015): VOL-2_ISSUE-05_May_2015 Vlsi Modelling of Side Channel Attacks on Modern Cache Based Processors Abstract   PDF
mukku Dinesh Kumar, g. Dilli Rani, V. Trimurthulu
 
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